Lisa Wu Wills

Curriculum Vitae

Research Interests

Computer architecture, energy-efficient computing, performance analysis, accelerator architecture, mapping compute- or memory-intensive applications onto existing and novel architectures, hardware-software co-designs, domain-specific applications and accelerators, emerging applications related to big data, graph analytics, healthcare, genomic processing, and areas that have a direct impact on improving human lives.

Current
Position
Duke University, Durham, NC
Clare Boothe Luce Assistant Professor,
Computer Science and Electrical and Computer Engineering (starting July 2019)

Education
University of California, Berkeley, CA
Postdoctoral Researcher, Electrical Engineering and Computer Science

Research Sponsor: Professor Krste Asanović

Research Mentor: Professor David Patterson

Columbia University, New York, NY, May 2014
PhD, Computer Science

Research Advisor: Professor Martha Kim

Dissertation: Accelerating Similarly-Structured Data

 

University of Michigan, Ann Arbor, MI
Master of Science, Computer Science and Engineering

Research Advisor: Professor Todd Austin​

Master's Thesis: A Fast and Flexible Architecture for Secure Communication

 

University of Illinois, Urbana-Champaign, IL
Bachelor of Science, Electrical and Computer Engineering
Honors and Awards
IEEE International Symposium of Microarchiteture (MICRO) Best Paper Award 2016 
  for Graphcionado​
 
IEEE Micro Top Picks 2015
  for Q100: A Database Processing Unit
 
ACM Architectural Support for Programming Languages and Operating Systems (ASPLOS) Best Paper Nominee 2014
  for Q100: A Database Processing Unit
IEEE Micro Top Picks 2014
  for Hardware Accelerated Range Partitioner
IEEE Computer Architecture Letters (CAL) Best of CAL Paper Award 2011 
  for Cache Impacts of Datatype Acceleration

 
Publications

Conference Papers

Lisa Wu, David Bruns-Smith, Frank A. Nothaft, Qijing Huang, Sagar Karandikar, Johnny Le, Andrew Lin, Howard Mao, Brendan Sweeney, Krste Asanović, David A. Patterson, and Anthony D. Joseph, "FPGA Accelerated INDEL Realignment in the Cloud". To appear in the IEEE International Symposium on High-Performance Computer Architecture (HPCA) 2019. 
 
Tae Jun Ham, Lisa Wu, Narayanan Sundaram, Nadathur Rajagopalan Satish, and Margaret Martonosi, "Graphicionado: High-Performance and Energy-Efficient Accelerator for Graph Analytics". International Symposium on Microarchitecture (MICRO) 2016. Awarded Best Paper. IEEE Micro Top Picks Honorable Mention.
 
Lisa Wu, Andrea Lottarini, Timothy K. Paine, Martha A. Kim, and Kenneth A. Ross, "Q100: The Architecture and Design of a Database Processing Unit". ACM Architectural Support for Programming Languages and Operating Systems (ASPLOS) 2014. Best Paper Nominee. IEEE Micro Top Picks.
 
Lisa Wu, Raymond J. Barker, Martha A. Kim, and Kenneth A. Ross, "Navigating Big Data with High-Throughput Energy-Efficient Data Partitioning". International Symposium on Computer Architecture (ISCA) 2013. IEEE Micro Top Picks.
 
Lisa Wu, Martha A. Kim, and Stephen A. Edwards, "Cache Impacts of Datatype Acceleration". IEEE Computer Architecture Letters (CAL) 2011. Best of CAL. 
 
Chris Weaver, Rajeev Krishna, Lisa Wu, and Todd Austin, "Application Specific Architectures: A Recipe for Fast, Flexible, and Power Efficient Designs." International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) 2001. 
 
Lisa Wu, Chris Weaver, and Todd Austin, "Cryptomaniac: A Fast Flexible Architecture for Secure Communication". International Symposium on Computer Architecture (ISCA) 2001.
 
Journal Papers
 
Lisa Wu, Andrea Lottarini, Timothy K. Paine, Martha A. Kim, and Kenneth A. Ross, "The Q100 Database Processing Unit". IEEE Micro Top Picks, Volume 35, Issue 3, May-June 2015.
 
Lisa Wu, Orestis Polychroniou, Raymond J. Barker, Martha A. Kim, and Kenneth A. Ross, "Energy Analysis of Hardware and Software Range Partitioning". ACM Transaction on Computer Systems (TOCS), Volume 32, Number 3, September 2014. Invited Article.
 
Lisa Wu, Raymond J. Barker, Martha A. Kim, and Kenneth A. Ross, "Hardware Partitioning for Big Data Analytics". IEEE Micro Top Picks, Volume 34, Issue 3, May-June 2014.
 
Workshop Papers
 
Lisa Wu, Frank A. Nothaft, Brendan Sweeney, David Bruns-Smith, Sagar Karandikar, Johnny Le, Howard Mao, Krste Asanović, David A. Patterson, and Anthony D. Joseph, "Accelerating Duplicate Marking in the Cloud". HPCA Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB) 2018.
 
Lisa Wu and Martha A. Kim, "Acceleration Targets: A Study of Popular Benchmark Suites". Dark Silicon Workshop (DaSi) 2012, held in conjunction with ISCA 2012.
 
Patents
Lisa K. Wu, Tae Jun Ham, Nadathur Rajagopalan Satish, and Narayanan Sundaram, "Instructions, Circuits, and Logic for Graph Analytics Acceleration". United States Patent Application No. 20170286122; filed October 2017.
Jesus Corbal, Roger Espasa Sans, Milind B. Girkar, Lisa K. Wu, Dennis R. Bradford, and Victor W. Lee, "System, Apparatus, and Method for Aligning Registers". United States Patent Application No. 2012254589; filed October 2012.
Jesus Corbal, Bret L. Toll, Robert C. Valentine, Jeffrey G. Wiedemeier, Sirdhar Samudrala, Milind B. Girkar, Thomas A. Forsyth, Elmoustapha Ould-Ahmed-Vall, Dennis R. Bradford, and Lisa K. Wu, "Systems, Apparatuses, and Methods for Blending Two Source Operands into a Single Destination Using a Writemask". United States Patent Application No. 20120254588; filed October 2012.
Jesus Corbal, Andrew T. Forsyth, Thomas D. Fletcher, Lisa K. Wu, and Eric Sprangle, "Super multiply add (super MADD) instructions with three scalar terms". United States Patent No. 9792115; filed December 2011 and issued October 2017.
Edward T. Grochowski, Dennis R. Bradford, George Z. Chrysos, Andrew T. Forsyth, Michael D. Upton, and Lisa K. Wu, "Apparatus and method for efficient gather and scatter operations". United States Patent No. 9785436; filed September 2012 and issued October 2017.
Robert C. Valentine, Jesus Corbal, Roger Espasa Sans, Robert D. Cavin, Bret L. Toll, Satiago Glalan Duran, Jeffrey G. Wiedemeier, Sridhar Samudrala, Milind B. Girkar, Edward T. Grochowski, Jonathan C. Hall, Dennis R. Bradford,  Elmoustapha Ould-Ahmed-Vall, James C. Abel, Mark Charney, Seth Abraham, Suleyman Sair, Thomas A. Forsyth, Lisa Wu, and Charles Yount, "Vector friendly instruction format and execution thereof". United States Patent No. 9513917; filed January 2014 and issued December 2016.
Jesus Corbal, Andrew T. Forsyth, Lisa K. Wu, and Thomas D. Fletcher, "Instruction and logic to provide vector linear interpolation functionality". United States Patent No. 9766886; filed December 2011 and issued September 2017.
Jesus Corbal, Lisa K. Wu, George Z. Chrysos, Andrew T. Forsyth, and Ramacharan Sundararaman, "Prefetch with request for ownership without data". United States Patent No. 9430389; filed December 2011 and issued August 2016.
Research
Experience
Postdoctoral Researcher – ASPIRE and ADEPT Labs – University of California Berkeley (Fall 2016 to Summer 2019)

Research sponsor: Professor Krste Asanović

Research mentor: Professor David Patterson
 

Accelerating Genomics using AWS EC2 F1 Instances. Architected, designed, and deployed a high performing hardware accelerated genomic analytics system on FPGAs in the cloud.

Accelerator Composition Framework for FPGAs in the Cloud.

Research Scientist – Intel Labs – Santa Clara, CA (Fall 2014 to Fall 2016)

Accelerator for Graph Analytics. Led a research project to architect and design an efficient, reconfigurable, domain-specific hardware accelerator that can process graph analytics workloads with orders of magnitude in efficiency compared to optimized software.
Accelerating Dense and Sparse Matrix Operations using Specialization.

 
Research Assistant – The Architecture and Design (ARCADE) Lab – Columbia University (Fall 2010 to Summer 2014)

Research advisor: Professor Martha Kim
 

Database Processing Units (DPUs). Architected and designed a specific instance of a stream-based DPU for efficient processing of analytic database workloads.
Hardware Accelerated Data Partitioner. Architected and designed an efficient hardware accelerated data partitioner that can be used for workloads that exhibit divide-and-conquer or map-reduce computation.
Datatype Acceleration. Architected Abstract Datatype Instructions (ADIs) for hash tables and sparse vectors and showed promising potential for accelerating datatypes.
Mentoring
Experience
Graduate Research Mentor
Guided graduate students to work on research projects or supervised them to work on product development
David Bruns-Smith (Fall 2017 to Present)

UC Berkeley, EECS PhD candidate advised by Krste Asanović

Projects: Accelerating genomic analytics, Accelerator composer
Eric Love (Fall 2014 to Fall 2016, Spring 2019)

UC Berkeley, EECS PhD candidate advised by Krste Asanović

Master's Thesis: Ressort -- An Auto-Tuning Framework for Parallel Shuffle Kernels
Project: Autotuning for database query executions
Tae Jun Ham (Summer and Fall 2015)

Princeton University, EE PhD 2018 advised by Margaret Martonosi

Now: Postdoctoral researcher at Seoul National University 

Project: Accelerating graph analytics (intern at Intel Labs)
Andrea Pellegrini (Summer 2011)

University of Michigan Ann Arbor, EECS PhD 2013 advised by Valeria Bertacco

Now: Computer engineer at ARM

Project: Path-finding for Many Integrated Cores architecture for HPC applications (intern at Intel Xeon Phi product development team)
Eric Hill (Summer 2005)

University of Wisconsin Madison, EE PhD 2008 advised by Mikko Lipasti

Now: Computer architect at Intel

Project: Performance validation for Xeon servers (intern at Intel Xeon Server product development team)
Undergraduate Research Mentor
Guided undergraduate students to work on research projects
Brendan Sweeney (Fall 2017 to Present)

UC Berkeley, EECS 2021

Projects: Accelerating genomic analytics, Accelerator composer
Johnny Le (Spring 2017 to Fall 2017)

UC Berkeley, EECS MS 2018

Projects: Accelerating genomic analytics
Andrew Lin (Summer 2017)

UC Berkeley, EECS 2017

Now: CPU performance architect at Apple

Projects: Accelerating genomic analytics
Timothy Paine (Spring 2013 to Spring 2014)
Columbia University, Computer Engineering MS 2015
Now: Athena core developer at J.P. Morgan
Project: Accelerating database analytics
Teaching
Experience
Instructor/Lecturer
Duke University
CS/ECE 590 Computer Architecture and Hardware Acceleration Fall 2019

This course is a graduate-level seminar in computer architecture with special topics in hardware acceleration. This course surveys the landscape of hardware acceleration from historical contexts to recent trends in system designs spanning a variety of application domains. This course also covers the taxonomy of accelerators, the hardware-software co-designing of accelerators, and the deployment of accelerators using the AWS cloud.

University of California Berkeley
CS 252 Graduate Computer Architecture Spring 2017

This course is an introductory graduate-level course in computer architecture. This course provides the essential background for students intending to pursue research in computer architecture and related fields. This course also serves as preparation for the UC Berkeley EECS computer architecture oral prelim examination.

Teaching Assistant
Columbia University
CSEE 3827 Fundamentals of Computer Systems Fall 2011, Spring 2012

This course examines how the 1s and 0s that form the foundation of digital computing are organized, structured, and manipulated to produce full-fledged computer systems. In bridging this gap, the course will cover many subjects beginning with binary logic, combinatorial and sequential circuit design, memory structures, instruction set architectures, and, ultimately, basic processor design.

 
University of Michigan Ann Arbor
EECS 470 Computer Architecture

This course is an introductory graduate-level course in computer architecture. This course is intended to give students a solid, detailed understanding of how computers are designed and implemented, including the central processor and memory and I/O interfaces; and to make students aware of the numerous tradeoffs in design and implementation, their interaction, their realization in both historical and state-of-the-art systems, and trends that will affect them in future systems.

Talks
Invited University Seminars
 
Hardware Acceleration in the World of Emerging Applications (Spring 2019)
ADEPT Retreat at the University of California, Berkeley
CS Graduate Seminar at the University of North Carolina, Chapel Hill
CS/ECE Graduate Seminar at Duke University
CS Graduate Seminar at the University of British Columbia, Vancouver
CS/ECE Graduate Seminar at the University of California, Santa Barbara
ECE Graduate Seminar at the University of Texas, Austin
CS Graduate Seminar at Boston University
EE Graduate Seminar at Yale University
ESE Graduate Seminar at the University of Pennsylvania
 
Stories, not Words: How to Design Efficient Accelerators (Fall 2017)
ECE Graduate Seminar at Carnegie Mellon University (CMU)
 
Invited Industry Talks
 
Hardware Acceleration in the World of Emerging Applications (Summer/Fall 2019)
IBM T. J. Waston Research, Yorktown Heights, NY
Facebook, Boston, CA
Microsoft Research, Seattle, CA
Google, Mountain View, CA
Xilinx, San Jose, CA
Stories, not Words: How to Design Efficient Accelerators (Fall 2018)
Qualcomm Research, San Diego, CA
 
RISC-V: A Free and Open Instruction Set Architecture (Fall 2016)
Microsoft Research (MSR), Seattle, WA
 
Q100: The Architecture and Design of a Database Processing Unit (Summer 2014)
Intel Labs, Santa Clara, CA
Google, Mountainview, CA
NVIDIA Research, Santa Clara, CA
 
Conference Talks
 
FPGA Accelerated INDEL Realignment in the Cloud (Spring 2019)
International Symposium on High-Performance Computer Architecture (HPCA)
Unexpected yet Common: Industry after PhD (Fall 2018) Invited Speaker/Panelist
Grace Hopper Celebration (GHC) Career Panel
 
Accelerating Duplicate Marking in the Cloud (Spring 2018)
HPCA Workshop on Accelerator Architecture in Computational Biology and Bioinformatics (AACBB)
 
The Road Less Traveled? (Fall 2017) Invited Speaker
MICRO Workshop on Career for Women and Minorities in Computer Architecture
 
Q100: The Architecture and Design of a Database Processing Unit (Spring 2014)
ACM Architectural Support for Programming Languages and Operating Systems (ASPLOS)
 
Navigating Big Data with High-Throughput Energy-Efficient Data Partitioning (Summer 2013)
International Symposium on Computer Architecture (ISCA)
 
Acceleration Targets: A Study of Popular Benchmark Suites (Summer 2012)
ISCA Workshop on Dark Silicon (DaSi)
 
Cache Impacts of Datatype Acceleration (Fall 2011)
HPCA Special Session for Best of IEEE Computer Architecture Letters (CAL)
 
Crytomaniac: A Fast Flexible Architecture for Secure Communication (Summer 2001)
International Symposium on Computer Architecture (ISCA)
 
Guest Lectures
 
Hardware Specialization and Acceleration (Fall 2017)
CS 111 Computer Architecture at Mills College
 
X86 Instruction Set Architecture (Spring 2012)
CSEE 3827 Fundamentals of Computer Systems at Columbia University
 
Services
Conference Program Committee
 
International Symposium on Code Generation and Optimization (CGO) 2020
International Symposium on Workload Characterization (IISWC) 2019
International Symposium on Microarchitecture (MICRO) 2019
International Symposium on High-Performance Computer Architecture (HPCA) 2019
International Symposium on Microarchitecture (MICRO) 2017
International Symposium on Computer Architecture (ISCA) 2017
International Symposium on Code Generation and Optimization (CGO) 2017
International Symposium on Performance Analysis of Systems and Software (ISPASS) 2017
International Symposium on High-Performance Computer Architecture Industry Session (HPCA Industry Session) 2016
International Symposium on Computer Architecture (ISCA) 2016
International Symposium on Workload Characterization (IISWC) 2015
 
Conference External Review Committee
 
International Symposium on High-Performance Computer Architecture (HPCA) 2020
International Symposium on Computer Architecture (ISCA) 2019
International Symposium on High-Performance Computer Architecture (HPCA) 2018
International Symposium on Microarchitecture (MICRO) 2015
International Symposium on Computer Architecture (ISCA) 2015
 
Conference Organizing Committee
 
Industrial Liaison Chair: International Symposium on Workload Characterization (IISWC) 2017
Publicity Chair: International Symposium on Computer Architecture (ISCA) 2015
 
Book Reviews
 
Morgan & Claypool series on Computer Architecture: Compiling Algorithms for Heterogenous Systems (September 2017)
 
Journal Reviews

IEEE Micro: The Xbox One X Scorpio Engine (December 2017)
IEEE Micro: Emergent Behaviors in Internet of Things: The Ultimate Ultra-Large-Scale System (June and August 2016)
 
Work
Experience
Intel Corporation
 
Xeon Phi Core Architect and Performance Architect

Knights Hill application characterization and analyses of stencil and cloud workloads.

Knights Corner and Larrabee Vector Processing Unit (VPU) lead architect.

 
Xeon Performance Architect and Uncore Architect

Quantitative analysis of Xeon system performance.

Xeon QPI home agent architect.

 
Itanium Core Microarchitect and Performance Architect

Itanium Instruction Fetch Unit (IBox) microarchitect.

Quantitative analysis of Itanium core performance.

Performance modeling and projection of Itanium processor cores.

 
Graduate Rotation Engineer

Performance correlation and functional validation of Xeon multimedia instructions.

Application optimization for Xeon architectures.

Apple Inc.

Performance Intern  Quantitative analysis of Mac system performance.

 
Hewlett-Packard Company

Network Intern  WAN test lab development for business network solution services.


Advanced Micro Devices, Inc.

Product Intern  Post-silicon debug and characterization using Teradyne testers.

References
Krste Asanović
Professor, EECS Department, Computer Science Division
University of California Berkeley
Martha Kim
Associate Professor, Department of Computer Science
Columbia University
Todd Austin
Professor, EECS Department
University of Michigan Ann Arbor
Margaret Martonosi
Professor, Department of Computer Science
Princeton University

Contact

lisa at cs dot duke dot edu

LSRC Building • 308 Research Drive • Durham • NC • 27708

© 2019 by Lisa Wu Wills